1. Field of the Invention
The present invention relates to arithmetic units for computing systems and, more particularly, to floating point arithmetic units.
2. Description of Related Art
Many computer programs require a large number of floating point arithmetic operations. Consequently, a large number of the instructions executed by a computer in which such programs are run are floating point instructions. For such programs, the greater the number of floating point arithmetic instructions that can be executed per cycle, the faster the machine speed of operation.
The prior art is replete with examples of efforts to speed up floating point processing time. U.S. Pat. No. 4,683,547 to DeGroot, for example, discloses a floating point arithmetic unit which allows two floating point results to be produced each cycle. That same patent discusses prior art teachings of arithmetic units which allow multiple arithmetic operations to be executed at once. Yet another approach is shown in U.S. Pat. No. 4,075,704 to O'Leary, that approach involving constructing a two stage pipelined floating point adder.
Notwithstanding the teachings of the patents described above, and similar patents, nowhere is there known to be disclosed or suggested in the prior art an apparatus and method as described and claimed herein, which apparatus and method have highly desirable characteristics relating to system speed.